1. Field of the Invention
The present invention relates to a semiconductor device including an array section having a plurality of circuit blocks and a method for controlling such a semiconductor device. More particularly, the present invention relates to a semiconductor device having a function of cutting off a leakage current occurring in the array section for every circuit block individually.
2. Description of the Related Art
A redundant design technique (the defect compensation technique) has been employed to prevent the yield of a large-scale integration circuit (LSI) from decreasing due to random defects which may occur in the LSI during the semiconductor fabrication process. In the redundant design technique, a redundancy is established in the circuit configuration so that an occurrence of a small number of defects will not damage the function of the whole LSI. Such a redundant design technique is especially applied to memories.
For example, in memories such as a random access memory (RAM) and an erasable programmable read only memory (EPROM), a spare memory cell array is prepared in addition to a predetermined memory cell array (the main memory cell array). If a defect occurs in a portion of the main memory cell array, the spare memory cell array is used in place of the defective portion of the main memory cell array.
Such defect compensation under the redundant circuit design is realized by a fixed write method or a tester mounting method. In the fixed write method, a pre-mounted wafer is screened by an external tester in the fabrication stage. If a defective portion (e.g., a defective memory cell which does not normally operate) is found as a result of the screening, switching of the defective portion to a redundant circuit (e.g., a spare memory cell array or memory block) is accomplished. This switching includes, for example, cutting a programmable read only memory (PROM) wiring by applying a current or irradiating with laser light. The switching is accomplished by hardware at the final stage of the fabrication process and improves the production yield.
The screening for defective memory cells in the redundant circuit design is a so-called destructive test which is performed by an external tester during the fabrication process (i.e., for a pre-mounted wafer) by applying a voltage higher than a normal operational voltage to the wafer. Therefore, in the case where a control circuit portion (such as a chip logic) is formed on one chip together with a memory circuit, the control circuit portion may be adversely affected by the screening. Moreover, devices mounted on the chip need to have a durability against the screening voltage. To avoid these problems, the tester mounting method is often employed, where a tester for detecting a defective memory cell is mounted on each chip to avoid the screening.
In the tester mounting method, an internal tester mounted in an LSI is used for detecting a defective memory cell, and to switch the defective memory cell to a redundant circuit based on the test result if necessary. Such a test is automatically performed when the device is turned on (self-checking). The test result is stored in a volatile memory and the switching is accomplished by software.
The registration of the switching will be described more specifically using the case of the fixed write method as an example.
The switching of a defective portion and a spare memory cell array described above can be accomplished by a current fuse method, a laser fuse method, a method where high-resistance polysilicon is short-circuited by laser irradiation, a method where a polysilicon diode is short-circuited, and the like. In the current fuse method, a PROM fuse (made of polysilicon, for example) is melted (thereby "blowing" the fuse) by Joule heating generated by current flow. In the laser fuse method, a PROM fuse (made of polysilicon, for example) is melted by spot irradiation with a laser beam. In this method, a laser-blown type fuse ROM is used. If a defective memory cell is found during testing, the position of the fuse to be cut off (the "cut-off" fuse) is determined from the address of the defective memory cell. Based on the determined position information, the position of the laser beam irradiation is controlled so as to melt the fuse. The information regarding the state of the defective memory cell is thus written in the fuse ROM. With this information, when a line corresponding to the cutoff fuse is accessed, the line is connected to the spare memory cell array, not to the main memory cell array, thereby accomplishing the switching. Thus, the element which switches the defective element to the spare element functions as a decoder.
In the tester mounting method, as in the fixed write method, the test result from the internal tester is stored in a volatile memory, and the access is switched to the spare memory cell array depending on the stored test result. For example, the addresses of defective memory cells are stored, and the address of a memory cell which is requested for accessing is compared with the stored addresses of the defective memory cells. When it is determined that one of the defective memory cells is requested for accessing, the spare memory cell array (the redundant memory cell array), not the main memory cell array, is accessed. This prohibits the access to any defective memory cell or the memory cell array including the defective memory cell, and instead allows for the access to the redundant memory cell array.
Thus, in the redundant circuit design as described above, the defect compensation is realized by prohibiting the access to a defective memory cell and switching to a replacement cell. This successfully compensates the memory function of the defective memory cell in the main memory cell array. However, there arises a problem when a leakage current occurs from a defective memory cell in the memory cell array due to, for example, a short circuit in the defective memory cell or gate floating by the cutting of the defective memory cell. In such a case, though the access to the defective memory cell is prohibited, a defective status of the memory cell array due to the leakage current cannot be compensated for because the defective memory cell is kept electrically connected with the power source. Such a leakage current is not detected even in the self-checking described above. Moreover, a leakage current may sometimes occur in a memory cell which is effective in the memory function and is not necessarily defective.
When such a leakage current is present in the semiconductor device, waste power is consumed. This wasteful power consumption due to the leakage current creates a critical problem especially in a portable information apparatus where a secondary battery is used for back-up operation, for example. In such a case, system failure may possibly arise due to the leakage current.